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C8051F54X Datasheet(PDF) 49 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 49 Page - Silicon Laboratories |
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49 / 276 page  C8051F54x Rev. 1.1 49 Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) IDD 4 VDD = 2.1 V, F = 200 kHz — 50 — µA VDD = 2.1 V, F = 1.5 MHz — 410 — µA VDD = 2.1 V, F = 25 MHz — 6.5 8.0 mA VDD = 2.1 V, F = 50 MHz — 13 16 mA IDD 4 VDD = 2.6 V, F = 200 kHz — 67 — µA VDD = 2.6 V, F = 1.5 MHz — 530 — µA VDD = 2.6 V, F = 25 MHz — 8.0 15 mA VDD = 2.6 V, F = 50 MHz — 16 25 mA IDD Supply Sensitivity 4 F = 25 MHz — 55 — %/V F = 1 MHz — 58 — IDD Frequency Sensitivity 4.6 VDD = 2.1V, F < 12.5 MHz, T = 25 °C — 0.26 — mA/MHz VDD = 2.1V, F > 12.5 MHz, T = 25 °C — 0.26 — VDD = 2.6V, F < 12.5 MHz, T = 25 °C — 0.34 — VDD = 2.6V, F > 12.5 MHz, T = 25 °C — 0.34 — Digital Supply Current4 (Stop or Suspend Mode) Oscillator not running, VDD Monitor Disabled µA Temp = 25 °C— 1 — Temp = 60 °C— 6 — Temp= 125 °C— 70 — Table 6.2. Global Electrical Characteristics (Continued) –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max Units Notes: 1. Given in Table 6.4 on page 52. 2. VIO should not be lower than the VDD voltage. 3. SYSCLK must be at least 32 kHz to enable debugging. 4. Guaranteed by characterization. Does not include oscillator supply current. 5. IDD estimation for different frequencies. 6. Idle IDD estimation for different frequencies. |
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