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C8051F54X Datasheet(PDF) 50 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 50 Page - Silicon Laboratories |
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50 / 276 page  C8051F54x 50 Rev. 1.1 Figure 6.1. Minimum VDD Monitor Threshold vs. System Clock Frequency Note: With system clock frequencies greater than 25 MHz, the VDD monitor level should be set to the high threshold (VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used with an external regulator powering VDD directly. See Figure 9.2 on page 73 for the recommended power supply connections. |
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