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C8051F54X Datasheet(PDF) 70 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 70 Page - Silicon Laboratories |
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70 / 276 page  C8051F54x Rev. 1.1 69 8.1. Comparator Multiplexer C8051F54x devices include an analog input multiplexer for each of the comparators to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Defini- tion 8.5). The CMX0P3–CMX0P0 bits select the Comparator0 positive input; the CMX0N3–CMX0N0 bits select the Comparator0 negative input. Similarly, the Comparator1 inputs are selected in the CPT1MX reg- ister using the CMX1P3-CMX1P0 bits and CMX1N3-CMX1N0 bits. The same pins are available to both multiplexers at the same time and can be used by both comparators simultaneously. Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con- figured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “18.6. Special Function Registers for Accessing and Configuring Port I/O” on page 161). Figure 8.3. Comparator Input Multiplexer Block Diagram VDD + - GND CPn + CPn - P0.1 P0.3 P0.5 P0.7 CMXnN3 CMXnN2 CMXnN1 CMXnN0 CMXnP3 CMXnP2 CMXnP1 CMXnP0 P1.1 P1.3 P1.5 P1.7 P2.1 P2.3 P2.5 P2.7 P0.0 P0.2 P0.4 P0.6 P1.0 P1.2 P1.4 P1.6 P2.0 P2.2 P2.4 P2.6 |
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