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C8051F54X Datasheet(PDF) 15 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 15 Page - Silicon Laboratories |
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15 / 276 page  C8051F54x Rev. 1.1 15 Figure 1.2. C8051F542/3/6/7 Block Diagram Digital Peripherals UART0 Timers 0, 1, 2, 3 6 channel PCA/WDT LIN 2.1 Priority Crossbar Decoder P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Crossbar Control Port I/O Configuration SFR Bus P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 I2C Debug / Programming Hardware Power On Reset Reset C2CK/RST P1.6 P1.7 Analog Peripherals Comparator 0 + - 12-bit 200ksps ADC A M U X VREF VDD VDD VREF GND CP0, CP0A Voltage Reference VREF System Clock Setup External Oscillator XTAL1 CIP-51 8051 Controller Core (50 MHz) 16 kB Flash Program Memory 256 Byte RAM Port 0 Drivers Port 1 Drivers Voltage Regulator (LDO) GND VREGIN VDD XTAL2 VIO P2.0 P2.1/C2D Port 2 Drivers Temp Sensor P0 – P2 GNDA Clock Multiplier Internal Oscillator (±0.5%) 1 kB XRAM SPI Comparator 1 + - CP1, CP1A C2D |
Similar Part No. - C8051F54X |
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Similar Description - C8051F54X |
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