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C8051F54X Datasheet(PDF) 18 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 18 Page - Silicon Laboratories |
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18 / 276 page  C8051F54x Rev. 1.1 18 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F54x Name Pin ‘F540/1/4/5 (32-pin) Pin ‘F542/3/6/7 (24-pin) Type Description VDD 4 3 Digital Supply Voltage. Must be connected. GND 6 4 Digital Ground. Must be connected. VDDA 5 — Analog Supply Voltage. Must be connected. Connected internally to VDD on the 24-pin packages. GNDA 7 5 Analog Ground. Must be connected. VREGIN 3 2 Voltage Regulator Input VIO 2 1 Port I/O Supply Voltage. Must be connected. RST/ C2CK 10 8 D I/O D I/O Device Reset. Open-drain output of internal POR or VDD Monitor. Clock signal for the C2 Debug Interface. P2.1/ C2D — 7 D I/O or A In D I/O Port 2.1. See SFR Definition 18.20 for a description. Bi-directional data signal for the C2 Debug Interface. P3.0/ C2D 9 — D I/O or A In D I/O Port 3.0. See SFR Definition 18.24 for a description. Bi-directional data signal for the C2 Debug Interface. P0.0 8 6 D I/O or A In Port 0.0. See SFR Definition 18.12 for a description. P0.1 1 24 D I/O or A In Port 0.1 P0.2 32 23 D I/O or A In Port 0.2 P0.3 31 22 D I/O or A In Port 0.3 P0.4 30 21 D I/O or A In Port 0.4 P0.5 29 20 D I/O or A In Port 0.5 P0.6 28 19 D I/O or A In Port 0.6 P0.7 27 18 D I/O or A In Port 0.7 P1.0 26 17 D I/O or A In Port 1.0. See SFR Definition 18.16 for a description. P1.1 25 16 D I/O or A In Port 1.1. P1.2 24 15 D I/O or A In Port 1.2. |
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