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C8051F54X Datasheet(PDF) 28 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 28 Page - Silicon Laboratories |
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28 / 276 page  C8051F54x 28 Rev. 1.1 Figure 4.6. QFN-24 Landing Diagram Table 4.6. QFN-24 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 3.90 4.00 X2 2.70 2.80 C2 3.90 4.00 Y1 0.65 0.75 E 0.50 BSC Y2 2.70 2.80 X1 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. |
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