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C8051F54X Datasheet(PDF) 29 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 29 Page - Silicon Laboratories |
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29 / 276 page  C8051F54x Rev. 1.1 29 5. 12-Bit ADC (ADC0) The ADC0 on the C8051F54x consists of an analog multiplexer (AMUX0) with 25/18 total input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, pro- grammable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0 sub- system has a special Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Func- tion Registers shows in Figure 5.1. ADC0 inputs are single-ended and may be configured to measure P0.0-P3.7, the Temperature Sensor output, VDD, or GND with respect to GND. The voltage reference for ADC0 is selected as described in Section “6.2. Temperature Sensor” on page 60. ADC0 is enabled when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are taking place. Figure 5.1. ADC0 Functional Block Diagram ADC0CN Start Conversion VDD 28-to-1 AMUX0 VDD P0.0 P0.7 P1.0 P1.7 ADC0MX GND Temp Sensor ADC0TK Burst Mode Logic Start Conversion Burst Mode Oscillator 25 MHz Max SYSCLK P2.2-P2.7, P3.0 available on 32-pin packages 00 AD0BUSY (W) 10 CNVSTR Input Timer 2 Overflow 11 01 Timer 1 Overflow 12-Bit SAR ADC 32 ADC0LTH AD0WINT ADC0LTL ADC0GTH ADC0GTL ADC0CF Accumulator Window Compare Logic Selectable Gain P2.0 P2.7 P3.0 ADC0GNL ADC0GNH ADC0GNA |
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