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C8051F54X Datasheet(PDF) 31 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 31 Page - Silicon Laboratories |
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31 / 276 page  C8051F54x Rev. 1.1 31 Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is complete, ADC0 does not track the input. Rather, the sampling capacitor remains disconnected from the input making the input pin high-impedance until the next convert start signal. Dual-Tracking Mode is selected when AD0TM is set to 11b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is complete, ADC0 tracks continuously until the next con- version is started. Depending on the output connected to the ADC input, additional tracking time, more than is specified in Table 6.9, may be required after changing MUX settings. See the settling time requirements described in Section “5.2.1. Settling Time Requirements” on page 34. Figure 5.2. ADC0 Tracking Modes 5.1.3. Timing ADC0 has a maximum conversion speed specified in Table 6.9. ADC0 is clocked from the ADC0 Subsys- tem Clock (FCLK). The source of FCLK is selected based on the BURSTEN bit. When BURSTEN is logic 0, FCLK is derived from the current system clock. When BURSTEN is logic 1, FCLK is derived from the Burst Mode Oscillator, an independent clock source with a maximum frequency of 25 MHz. When ADC0 is performing a conversion, it requires a clock source that is typically slower than FCLK. The ADC0 SAR conversion clock (SAR clock) is a divided version of FCLK. The divide ratio can be configured using the AD0SC bits in the ADC0CF register. The maximum SAR clock frequency is listed in Table 6.9. ADC0 can be in one of three states at any given time: tracking, converting, or idle. Tracking time depends on the tracking mode selected. For Pre-Tracking Mode, tracking is managed by software and ADC0 starts conversions immediately following the convert start signal. For Post-Tracking and Dual-Tracking Modes, the tracking time after the convert start signal is equal to the value determined by the AD0TK bits plus 2 FCLK cycles. Tracking is immediately followed by a conversion. The ADC0 conversion time is always 13 SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion. Figure 5.3 shows timing diagrams for a conversion in Pre-Tracking Mode and tracking plus conversion in Post-Tracking or Dual-Tracking Mode. In this example, repeat count is set to one. Convert Start Post-Tracking AD0TM= 01 Track Convert Idle Idle Track Convert.. Pre-Tracking AD0TM = 10 Track Convert Track Convert ... Dual-Tracking AD0TM = 11 Track Convert Track Track Track Convert.. |
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