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C8051F54X Datasheet(PDF) 38 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 38 Page - Silicon Laboratories |
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38 / 276 page  C8051F54x 38 Rev. 1.1 Indirect Address = 0x04; Indirect Address = 0x07; Gain Register Definition 5.1. ADC0GNH: ADC0 Selectable Gain High Byte Bit 7 6 5 4 3 2 1 0 Name GAINH[7:0] Type W Reset 1 1 1 1 1 1 0 0 Bit Name Function 7:0 GAINH[7:0] ADC0 Gain High Byte. See Section 5.3.1 for details on calculating the value for this register. Note: This register is accessed indirectly; See Section 5.3.2 for details for writing this register. Gain Register Definition 5.2. ADC0GNL: ADC0 Selectable Gain Low Byte Bit 7 6 5 4 3 2 1 0 Name GAINL[3:0] Reserved Reserved Reserved Reserved Type W W W W W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7:4 GAINL[3:0] ADC0 Gain Lower 4 Bits. See Figure 5.3.1 for details for setting this register. This register is only accessed indirectly through the ADC0H and ADC0L register. 3:0 Reserved Must Write 0000b Note: This register is accessed indirectly; See Section 5.3.2 for details for writing this register. |
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