TNETV2685FIBZUT7 datasheet(171/191 Pages) TI1

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TMS320DM647

TMS320DM648

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SPRS372H – MAY 2007 – REVISED APRIL 2012

6.19.4 Ethernet Subsystem Timing

Table 6-82. Ethernet Subsystem Timing Requirements

PARAMETER(1)

MIN

NOM

MAX

UNITS

t01

REFCLKP/N period, mode

x 10 mode

x 20 mode

x 25 mode

t02

REFCLKP/N duty cycle

t03

REFCLKP/N rise/fall

700

t04

PLL Clock Period, x n Mode

t01 / n

t05

PLL power up

1 + 200 * C

μs

(1)

C = REFCLKP/N period in

μs.

REFCLKP/N Jitter and PLL Loop Bandwidth

Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby

impairing system performance. A good quality, low jitter reference clock is necessary to achieve

compliance with most if not all physical layer standards (see Table 6-83).

Table 6-83. REFCLKP/N Jitter Requirements for Standards Compliance

Standard

Line Rate (Gbps)

Total REFCLKP/N Jitter (within PLL bandwidth)

Gigabit Ethernet

1.25

50 ps pk-pk

Peripheral Information and Electrical Specifications

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