TNETV2685FIBZUT7 datasheet(140/191 Pages) TI1

140 / 191 page

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

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Table 6-67. Switching Characteristics for Host-Port Interface Cycles(1) (2)

(see Figure 6-40 through Figure 6-47)

720, 800, 900, 1100

NO.

PARAMETER

UNIT

MIN

MAX

Case 1. HPIC or HPIA read

Case 2. HPID read with no auto-

9 × M + 20

increment(3)

Delay time, HSTROBE low to

Case 3. HPID read with auto-increment

td(HSTBL-HDV)

9 × M + 20

DSP data valid

and read FIFO initially empty(3)

Case 4. HPID read with auto-increment

and data previously prefetched into the

read FIFO

tdis(HSTBH-HDV)

Disable time, HD high-impedance from HSTROBE high

ten(HSTBL-HD)

Enable time, HD driven from HSTROBE low

td(HSTBL-HRDYH)

Delay time, HSTROBE low to HRDY high

td(HSTBH-HRDYH)

Delay time, HSTROBE high to HRDY high

Case 1. HPID read with no auto-

10 × M + 20

increment(3)

Delay time, HSTROBE low to

td(HSTBL-HRDYL)

HRDY low

Case 2. HPID read with auto-increment

10 × M + 20

and read FIFO initially empty(3)

td(HDV-HRDYL)

Delay time, HD valid to HRDY low

Case 1. HPIA write(3)

5 × M + 20

Delay time, HSTROBE high to

td(DSH-HRDYL)

Case 2. HPID write with no auto-

HRDY low

5 × M + 20

increment(3)

Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not

td(HSTBL-HRDYL)

40 × M + 20

empty(3)

td(HASL-HRDYH)

Delay time, HAS low to HRDY high

(1)

M = SYSCLK3 period = 6/CPU clock frequency in ns.

(2)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3)

Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.

140

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