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ST10F273Z4 Datasheet(PDF) 78 Page - STMicroelectronics |
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ST10F273Z4 Datasheet(HTML) 78 Page - STMicroelectronics |
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78 / 188 page  Watchdog timer ST10F273Z4 78/188 19 Watchdog timer The watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The watchdog timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. Each of the different reset sources is indicated in the WDTCON register: ● Watchdog timer reset in case of an overflow ● Software Reset in case of execution of the SRST instruction ● Short, long and power-on reset in case of hardware reset (and depending of reset pulse duration and RPD pin configuration) The indicated bits are cleared with the EINIT instruction. The source of the reset can be identified during the initialization phase. The watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced The Table 48 and Table 49 show the watchdog time range for 40 MHz and 64 MHz CPU clock respectively. Table 48. WDTREL reload value (fCPU = 40 MHz) Reload value in WDTREL Prescaler for fCPU = 40 MHz 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’) FFh 12.8 µs 819.2 µs 00h 3.277ms 209.7ms Table 49. WDTREL reload value (fCPU = 64 MHz) Reload value in WDTREL Prescaler for fCPU = 64 MHz 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’) FFh 8 µs 512 µs 00h 2.048ms 131.1ms |
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