ST72345C4 datasheet(107/247 Pages) STMICROELECTRONICS

107 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

107/247

11.3.4

Low-power modes

11.3.5

Interrupts

Note:

The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8:

Interrupts). These events generate an interrupt if the corresponding Enable Control Bit is set

and the interrupt mask in the CC register is reset (RIM instruction).

Table 47.

Low-power mode description

Mode

Description

Wait

No effect on 16-bit timer.

Timer interrupts cause the Device to exit from Wait mode.

Halt

16-bit timer registers are frozen.

In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from

the previous count when the Device is woken up by an interrupt with “exit from Halt mode”

capability or from the counter reset value when the Device is woken up by a reset.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is

armed. Consequently, when the Device is woken up by an interrupt with “exit from Halt

mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt

mode is captured into the ICiR register.

Table 48.

Interrupt events

Interrupt event

Event

flag

Enable

control bit

Exit from

Wait

Exit from

Halt

Input Capture 1 event/Counter reset in PWM mode

ICF1

ICIE

Yes

Input Capture 2 event

ICF2

Yes

Output Compare 1 event (not available in PWM mode)

OCF1

OCIE

Yes

Output Compare 2 event (not available in PWM mode)

OCF2

Yes

Timer overflow event

TOF

TOIE

Yes

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