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ST72561J4-Auto Datasheet(PDF) 106 Page - STMicroelectronics |
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ST72561J4-Auto Datasheet(HTML) 106 Page - STMicroelectronics |
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106 / 324 page ![]() 16-bit timer ST72561-Auto 106/324 Doc ID 12370 Rev 8 Figure 47. Timer block diagram Figure 48. 16-bit read sequence: (from counter or alternate counter register) MCU-PERIPHERAL INTERFACE COUNTER ALTERNATE OUTPUT COMPARE REGISTER OUTPUT COMPARE EDGE DETECT OVERFLOW DETECT CIRCUIT 1/2 1/4 1/8 8-bit buffer ST7 INTERNAL BUS LATCH1 OCMP1 ICAP1 EXTCLK fCPU TIMER INTERRUPT ICF2 ICF1 TIMD 0 0 OCF2 OCF1 TOF PWM OC1E EXEDG IEDG2 CC0 CC1 OC2E OPM FOLV2 ICIE OLVL1 IEDG1 OLVL2 FOLV1 OCIE TOIE ICAP2 LATCH2 OCMP2 8 8 8 low 16 8 high 16 16 16 16 (Control Register 1) CR1 (Control Register 2) CR2 (Control/Status Register) 6 16 8 8 8 8 8 8 EXEDG TIMER INTERNAL BUS CIRCUIT1 EDGE DETECT CIRCUIT2 CIRCUIT 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 CC[1:0] COUNTER pin pin pin pin pin REGISTER REGISTER Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) (See note) CSR is buffered Read At t0 Read Returns the buffered LS Byte value at t0 At t0 + Δt Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte |
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