ST72561J4-Auto datasheet(184/324 Pages) STMICROELECTRONICS

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LINSCI serial communication interface (LIN master/slave)

ST72561-Auto

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Doc ID 12370 Rev 8

Note:

If the period desynchronization of the slave is +15% (slave too slow), the character “00h”

which represents a sequence of 9 low bits must not be interpreted as a break character (9

bits + 15% = 10.35). Consequently, a valid LIN Synch break must last at least 11 low bits.

LINSCI clock tolerance when synchronized

When synchronization has been performed, following reception of a LIN synch break, the

LINSCI, in LIN mode, has the same clock deviation tolerance as in SCI mode, which is

explained below:

During reception, each bit is oversampled 16 times. The mean of the 8th, 9th and 10th

samples is considered as the bit value.

Consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit.

The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one

start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%.

15.9.8

Clock deviation causes

The causes which contribute to the total deviation are:

●

DTRA: deviation due to transmitter error.

Note: The transmitter can be either a master or a slave (in case of a slave listening to the

response of another slave).

●

DMEAS: error due to the LIN Synch measurement performed by the receiver.

●

DQUANT: error due to the baud rate quantization of the receiver.

●

DREC: deviation of the local oscillator of the receiver: This deviation can occur during

the reception of one complete LIN message assuming that the deviation has been

compensated at the beginning of the message.

●

DTCL: deviation due to the transmission line (generally due to the transceivers)

All the deviations of the system should be added and compared to the LINSCI clock

tolerance:

DTRA + DMEAS +DQUANT + DREC + DTCL < 3.75%

Figure 86.

Bit sampling in reception mode

RDI LINE

Sample

clock

12345678910

11 12

sampled values

One bit time

6/16

7/16

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