Si5013-EVB

4

Rev. 1.0

RMS and peak-to-peak jitter on the CDR CLKOUT.

Thus, any jitter measured is jitter generated by the

CDR.

Jitter Transfer: Referring to Figure 3, this test requires a

pattern generator, a clock source (synthesizer signal

source), a modulation source, a jitter analyzer, and a

pulse generator (all unconnected high-speed outputs

must be terminated to 50

). During this test, the Jitter

Analyzer modulates the data pattern and data clock

reference. The modulated data clock reference is

compared with the CLKOUT of the CDR. Jitter on

CLKOUT relative to the jitter on the data clock reference

is plotted versus modulation frequency at predefined

jitter amplitudes.

Figure 3. Test Configuration for Jitter Tolerance, Transfer, and Generation

Jitter

Analyzer

Pattern

Analyzer

Pulse

Generator

Pattern

Generator

Modulation

Source

Synthesizer

Signal Source

3.3 V

REFCLK

(optional)

DATAIN

CLKOUT

DATAOUT

Scope

Si5013-EVB

REFCLK+

DATAIN+

DATAOUT+

CLKOUT+

GPIB

DATAOUT–

Clock

Data Clock+

FM

GPIB

GPIB

CLKOUT–

REFCLK–

DATAIN–

GPIB

–

+

+

–

+

–

+

–

+

–