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VND5E008ASP-E Datasheet(PDF) 20 Page - STMicroelectronics |
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VND5E008ASP-E Datasheet(HTML) 20 Page - STMicroelectronics |
20 / 33 page Application information VND5E008ASP-E 20/33 DocID023813 Rev 4 3 Application information Figure 15. Application schematic Note: Channel 2 has the same internal circuit as channel 1. 3.1 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2 2004 (E) table. 3.2 MCU I/Os protection When negative transients are present on the VCC line, the control pins are pulled negative to approximatly -1.5 V. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching-up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation 1 -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC - VIH) / IIHmax Calculation example: For VCCpeak = -1.5 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V 75 Ω ≤ Rprot ≤ 240 kΩ. Recommended values: Rprot = 10 kΩ, CEXT = 10 nF. |
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