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VND5E050ACKTR-E Datasheet(PDF) 12 Page - STMicroelectronics |
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VND5E050ACKTR-E Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 43 page  Electrical specifications VND5E050ACJ-E, VND5E050ACK-E 12/43 Doc ID 022515 Rev 2 K3 IOUT/ISENSE IOUT = 4 A; VSENSE =4 V; VCSD =0 V; Tj = -40°C...150°C Tj = 25°C...150°C 1969 1950 1990 1990 2210 2153 dK3/K3 (1) Current sense ratio drift IOUT = 4 A; VSENSE =4 V; VCSD =0 V; TJ = -40 °C to 150 °C -6 6 % ISENSE0 Analog sense leakage current IOUT = 0 A; VSENSE =0V; VCSD =5 V; VIN =0 V; Tj = -40°C...150°C 01 µA IOUT = 0 A; VSENSE =0V; VCSD =0 V; VIN =5 V; Tj = -40°C...150°C 02 IOUT = 2 A; VSENSE =0V; VCSD =5 V; VIN =5 V; Tj = -40°C...150°C 01 IOL Open load on-state current detection threshold VIN =5 V; 8 V <VCC <18V; ISENSE =5 µA 420 mA VSENSE Max analog sense output voltage IOUT = 4 A; VCSD =0 V 5 V VSENSEH Analog sense output voltage in fault condition(2) VCC =13V; RSENSE =3.9 KΩ 8V ISENSEH Analog sense output current in fault condition(2) VCC =13V; VSENSE =5 V 9 mA tDSENSE1H Delay response time from falling edge of CS_DIS pin VSENSE <4 V; 0.5 A < IOUT < 4 A; ISENSE =90% of ISENSEMAX (see Figure 4) 40 100 µs tDSENSE1L Delay response time from rising edge of CS_DIS pin VSENSE <4 V; 0.5 A < IOUT < 4 A; ISENSE =10% of ISENSEMAX (see Figure 4) 520 µs tDSENSE2H Delay response time from rising edge of INPUT pin VSENSE <4 V; 0.5 A < IOUT < 4 A; ISENSE =90% of ISENSEMAX (see Figure 4) 80 250 µs ΔtDSENSE2H Delay response time between rising edge of output current and rising edge of current sense VSENSE <4V; ISENSE = 90% of ISENSEMAX, IOUT = 90% of IOUTMAX IOUTMAX = 2A (see Figure 7) 40 µs tDSENSE2L Delay response time from falling edge of INPUT pin VSENSE <4 V; 0.5 A < IOUT < 4 A; ISENSE=10% of ISENSEMAX (see Figure 4) 80 250 µs 1. Parameter guaranteed by design; it is not tested. 2. Fault condition includes: power limitation, over temperature and open load off-state detection. Table 9. Current sense (8 V < VCC < 18 V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit |
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