WM8912 datasheet(117/129 Pages) CIRRUS

117 / 129 page

Production Data

WM8912

PD, Rev 4.1, February 2013

117

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

011 = 8

1XX = 16

000 recommended for high FREF

011 recommended for low FREF

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R118 (76h)

FLL Control

15:0

FLL_K [15:0]

0000_0000

_0000_000

Fractional multiply for FREF

(MSB = 0.5)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R119 (77h)

FLL Control

14:5

FLL_N [9:0]

01_0111_0

111

Integer multiply for FREF

(LSB = 1)

3:0

FLL_GAIN [3:0]

0000

FLL Gain applied to error

0000 = x 1 (Recommended value)

0001 = x 2

0010 = x 4

0011 = x 8

0100 = x 16

0101 = x 32

0110 = x 64

0111 = x 128

1000 = x 256

Recommended that these are not changed from

default.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R120 (78h)

FLL Control

4:3

FLL_CLK_REF

_DIV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down

to <=13.5MHz.

For lower power operation, the reference clock can be

divided down further if desired.

1:0

FLL_CLK_REF

_SRC [1:0]

FLL Clock source

00 = MCLK

01 = BCLK

10 = LRCLK

WM8912 Datasheet(PDF) 117 Page - Cirrus Logic

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