## Overview of the ADCMP561 The **ADCMP561** is a high-speed, ultra-fast voltage comparator manufactured by Analog Devices. It is designed for applications requiring precise timing and high-speed signal processing, utilizing **Differential PECL (Positive Emitter-Coupled Logic)** outputs. --- ### Key Technical Specifications | Feature | Specification | | :--- | :--- | | **Propagation Delay** | 700 ps (typical) | | **Input Type** | Differential | | **Output Type** | Differential PECL | | **Supply Voltage** | +5.0 V and -5.2 V (Dual Rail) | | **Rise/Fall Time** | 500 ps | | **Input Range** | -2.0 V to +3.0 V | | **Package** | 20-lead QSOP | --- ### Internal Functional Blocks The ADCMP561 consists of several critical electronic components integrated into its silicon: 1. **Input Stage:** A high-speed differential amplifier stage with low offset voltage and high common-mode rejection. It is designed to handle very fast-moving edges without significant distortion. 2. **Latch Function:** The device includes a latch-enable (LE) pin. When the latch is activated, the output is held at its current state regardless of changes at the input. This is essential for high-speed data acquisition. 3. **Hysteresis Control:** It features an internal programmable hysteresis which helps prevent multiple transitions (chatter) caused by noise on the input signal. 4. **PECL Output Driver:** The output stage is specifically designed to drive 50 $\Omega$ loads terminated to $V_{CC} - 2.0$ V, ensuring signal integrity over transmission lines. --- ### Pin Configuration Summary | Pin Name | Description | | :--- | :--- | | **$V_{CCI}$ / $V_{CCO}$** | Positive Supply for Input and Output stages. | | **$V_{EE}$** | Negative Supply (Typically -5.2 V). | | **$IN+$ / $IN-$** | Differential Analog Inputs. | | **$Q$ / $\bar{Q}$** | Differential PECL Outputs. | | **$LE$ / $\bar{LE}$** | Latch Enable differential inputs. | | **$HYS$** | Hysteresis control pin. | --- ### Typical Application Circuit When designing with the ADCMP561, the termination of the PECL outputs is critical. A standard configuration involves using 50 $\Omega$ resistors to a bias voltage. ```c // Concept: Standard PECL Output Termination [ADCMP561 Q] ----> [Transmission Line 50 Ohm] ----+---- [Receiver] | [50 Ohm Resistor] | [Vcc - 2.0V] ``` --- ### Primary Use Cases * **Automatic Test Equipment (ATE):** High-speed timing and pin electronics. * **High-Speed Data Communications:** Clock and data recovery. * **Threshold Detection:** Detecting ultra-short pulses in physics experiments or radar. * **Line Receivers:** Converting low-voltage differential signals to PECL levels.