The **LCMXO2-640HC-6TG100C** is a member of the **MachXO2** family developed by Lattice Semiconductor. It is categorized as an ultra-low-power, instant-on, non-volatile PLD (Programmable Logic Device) that bridges the gap between a CPLD and an FPGA. --- ## 1. Part Number Breakdown Understanding the nomenclature helps identify the specific capabilities of this component: | Code Segment | Meaning | Specification | |:---|:---|:---| | **LCMXO2** | Family Name | MachXO2 | | **640** | Density | 640 Look-Up Tables (LUTs) | | **HC** | Voltage/Speed | High Performance / 2.5V to 3.3V VCC | | **6** | Speed Grade | Grade 6 (Standard performance) | | **TG100** | Package Type | 100-pin TQFP (Thin Quad Flat Pack) | | **C** | Temp Grade | Commercial (0°C to 85°C) | --- ## 2. Key Technical Specifications The device is designed for system control functions, glue logic, and interface bridging. ### Core Resources * **LUTs:** 640 Look-Up Tables. * **User I/O:** 78 Maximum user I/O pins. * **Embedded Block RAM (EBR):** 18 Kbits. * **Distributed RAM:** 5 Kbits. * **Flash Memory:** User Flash Memory (UFM) available for non-volatile data storage. ### Electrical Characteristics * **Supply Voltage ($V_{CC}$):** 2.5V to 3.3V. * **I/O Standards:** Supports LVCMOS (3.3V, 2.5V, 1.8V, 1.5V, 1.2V), LVTTL, PCI, and differential signaling like LVDS. * **Power Consumption:** Extremely low standby power, typically in the micro-amp range. --- ## 3. Notable Features ### Non-Volatile "Instant-On" Unlike traditional FPGAs that require an external SPI Flash to load bitstreams at power-up, the MachXO2 stores its configuration in internal Flash. It is operational within milliseconds of power being applied. ### Hardened IP Cores To save LUT resources for custom logic, the device includes "Hard" (fixed-silicon) implementations of common functions: * **$I^2C$ Interfaces:** Two hardened controllers. * **SPI Interface:** One hardened controller. * **Timer/Counter:** 16-bit hardened timer. * **Oscillator:** Internal oscillator for clocking without external crystals. ### Dual Boot Support The device supports "Background Programming," allowing the device to remain operational while a new configuration is being loaded into the Flash memory. --- ## 4. Typical Applications Due to its small footprint and low power, it is commonly used for: 1. **System Power Sequencing:** Managing the power-up order of multi-rail SOCs. 2. **I/O Expansion:** Adding more GPIOs to a microcontroller via SPI or $I^2C$. 3. **Level Shifting:** Translating signals between different voltage domains (e.g., 1.2V to 3.3V). 4. **Interface Bridging:** Converting data between different serial or parallel protocols. ---