In the context of computer architecture, **SISC** usually refers to **Simple Instruction Set Computing** (or sometimes specifically the architecture used in educational "Simple Instruction Set Computer" models). Unlike CISC (Complex) or RISC (Reduced), SISC focuses on the absolute minimum hardware required to execute basic operations, making it ideal for learning logic design. --- ## 1. Core Hardware Components The electronic parts of a SISC processor are organized into the **Control Path** and the **Data Path**. ### Key Electronic Blocks | Component | Function | Electronic Implementation | | :--- | :--- | :--- | | **ALU (Arithmetic Logic Unit)** | Performs addition, subtraction, and logic gates (AND, OR). | Cascaded full-adders and logic gate arrays. | | **Registers** | Fast, temporary storage for operands and results. | Arrays of D-type Flip-Flops. | | **Control Unit (CU)** | Orchestrates the timing and signals for all other parts. | Finite State Machines (FSM) or microcode ROM. | | **Program Counter (PC)** | Holds the address of the next instruction. | A synchronous binary counter. | | **Instruction Register (IR)**| Stores the current instruction being decoded. | A parallel-in, parallel-out (PIPO) register. | --- ## 2. Bus Architecture SISC systems typically use a single-bus or dual-bus architecture to move data between electronic parts. * **Data Bus:** Traces on the PCB or internal silicon paths that carry the actual data (e.g., the number "5"). * **Address Bus:** Specifies where in the memory the data should be read from or written to. * **Control Lines:** Individual wires that signal components to "Read," "Write," or "Enable Output" (using Tri-state buffers). --- ## 3. Simplified Instruction Cycle The hardware interacts in a repetitive cycle driven by a **Crystal Oscillator (Clock)**: 1. **Fetch:** The PC sends an address to Memory; the Instruction is loaded into the IR. 2. **Decode:** The Control Unit interprets the bits in the IR to flip specific electronic switches. 3. **Execute:** The ALU performs the operation, and the result is stored back in a Register or Memory. --- ## 4. Hardware Logic Example If a SISC instruction is `ADD R1, R2`, the electronic sequence is: ```vhdl -- Conceptual Hardware Signal Logic Enable_R1_Out <= '1'; -- Put R1 data on the bus Enable_ALU_InA <= '1'; -- Send bus data to ALU Input A Enable_R2_Out <= '1'; -- Put R2 data on the bus Enable_ALU_InB <= '1'; -- Send bus data to ALU Input B ALU_Op <= "001"; -- Set ALU mode to 'Addition' Store_R1_In <= '1'; -- Capture ALU result back into R1 ```