1 Features
• High reliability enhanced product:
– Controlled baseline: one assembly and test
site, one fabrication site, extended product
lifecycle, extended product-change notification
and product traceability
• ADC Core:
– Resolution: 12 Bit
– Maximum sampling rate: 1.6 GSPS
– Non-interleaved architecture
– Internal dither reduces high-order harmonics
• Performance specifications (–1 dBFS):
– SNR (100 MHz): 57.4 dBFS
– ENOB (100 MHz): 9.1 Bits
– SFDR (100 MHz): 64 dBc
– Noise floor (–20 dBFS): –147 dBFS
• Full-scale input voltage: 800 mVPP-DIFF
• Full-power input bandwidth: 6 GHz
• JESD204C Serial data interface:
– Support for 2 to 8 total SerDes lanes
– Maximum baud-rate: 17.16 Gbps
– 64B/66B and 8B/10B encoding modes
– Subclass-1 support for deterministic latency
– Compatible with JESD204B receivers
• Optional internal sampling clock generation
– Internal PLL and VCO (7.2–8.2 GHz)
• SYSREF Windowing eases synchronization
• Four clock outputs simplify system clocking
– Reference clocks for FPGA or adjacent ADC
– Reference clock for SerDes transceivers
• Timestamp input and output for pulsed systems
• Power consumption (1 GSPS): 1.9W
• Power supplies: 1.1 V, 1.9 V

2 Applications
• Electronic warfare (SIGINT, ELINT)
• Satellite communications (SATCOM)

3 Description
ADC12QJ1600-EP is a quad channel, 12-bit, 1.6
GSPS analog-to-digital converters (ADC). Low power
consumption, high sampling rate and 12-bit resolution
makes the device suited for a variety of multi-channel
communications systems.
Full-power input bandwidth (-3 dB) of 6 GHz enables
direct RF sampling of of L-band and S-band.