General
The 74VHC138FT is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C
2MOS
technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (
Y0 -
Y7 )
will go low.
When enable input G1 is held low or either
G2A or
G2B is held high, decoding function is inhibited and all
outputs go high.
G1,
G2A , and
G2B inputs are provided to ease cascade connection and for use as an address decoder for memory
systems.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.

3. Features
(1) AEC-Q100 (Rev. H) (Note 1)
(2) Wide operating temperature: Topr = -40 to 125

(3) High speed: tpd = 5.7 ns (typ.) at VCC = 5 V
(4) Low power dissipation: ICC = 4.0
µA (max) at T
a = 25

(5) High noise immunity: VNIH = VNIL = 28 % VCC (min)
(6) Power down protection is provided on all inputs.
(7) Balanced propagation delays: tPLH
≈ tPHL
(8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
(9) Pin and function compatible with 74 series(AC/HC/AHC/LV etc.)138 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.