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XU316-1024-QF60B Datasheet (PDF) - Xmos Ltd.

XU316-1024-QF60B Datasheet PDF - Xmos Ltd.
Part # XU316-1024-QF60B
Download  XU316-1024-QF60B Download

File Size   2873.32 Kbytes
Page   83 Pages
Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.
Description XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)

XU316-1024-QF60B Datasheet (PDF)

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XU316-1024-QF60B Datasheet PDF - Xmos Ltd.

Part # XU316-1024-QF60B
Download  XU316-1024-QF60B Click to download

File Size   2873.32 Kbytes
Page   83 Pages
Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.
Description XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 60-QFN (7x7)

XU316-1024-QF60B Datasheet (HTML) - Xmos Ltd.

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XU316-1024-QF60B Product details

2 XU316-1024-QF60B Features
· Multicore Microcontroller with Advanced Multi-Core RISC Architecture
• 16 real-time logical cores on 2 xCORE tiles
• Cores share up to 1200 MIPS
— Up to 2400 MIPS in dual issue mode
— Up to 1200 MFLOPS
• Each logical core has:
— Guaranteed throughput of between 1/5 and 1/8 of tile MIPS
— 16x32bit dedicated registers
• 229 high-density 16/32-bit instructions
— All have single clock-cycle execution (except for divide)
— 32x32!64-bit MAC instructions for DSP, arithmetic and cryptographic functions
• Vector unit, capable of:
— up to eight word, 16 half-word, or 32 byte multiply-adds.
— quad complex multiply, or 256 bit-wide multiply-adds.
· USB PHY, fully compliant with USB 2.0 specication
· Application PLL with fractional control
· Programmable I/O
• 34 general-purpose I/O pins, congurable as input or output
— Up to 16 x 1bit port, 2 x 4bit port, 1 x 8bit port
— 1 xCONNECT link
• Port sampling rates of up to 60MHz with respect to an external clock
• 64 channel ends (32 per tile) for communication with other cores, on or off-chip
• 3.3V IO with programmable drive strength
· Memory
• 1MB internal single-cycle SRAM (512KB per tile) for code and data storage
• 8KB internal OTP (shared between tiles or split providing 4KB per tile) for application boot code
· Hardware resources
• 12 clock blocks (6 per tile)
• 20 timers (10 per tile)
• 8 locks (4 per tile)
· JTAG Module for On-Chip Debug
· Security Features
• Programming lock disables debug and prevents read-back of memory contents
• AES bootloader ensures secrecy of IP held on external ash memory
· Ambient Temperature Range
• 0 °C to 70 °C
· Speed Grade
• 24: 600 MHz; up to 2400 MIPS, 1200 MFLOP/s, 38.4 GMACC/s
· Power Consumption
• 300mA (typical)
· 60-pin QFN package 0.4mm pitch




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