FEATURES

  Access Times of 25ns (SRAM) and 70, 90ns(FLASH)

  Packaging

    • 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402)

    • 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Figure 2). Package to be developed.

  512Kx32 SRAM

  512Kx32 5V Flash

  Organized as 512Kx32 of SRAM and 512Kx32 of Flash Memory with common Data Bus

  Low Power CMOS

  Commercial, Industrial and Military Temperature Ranges

  TTL Compatible Inputs and Outputs

  Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

  Weight - 13 grams typical

FLASH MEMORY FEATURES

  100,000 Erase/Program Cycles

  Sector Architecture

    • 8 equal size sectors of 64KBytes each

    • Any combination of sectors can be concurrently erased. Also supports full chip erase

  5 Volt Programming; 5V ± 10% Supply

  Embedded Erase and Program Algorithms

  Hardware Write Protection

  Page Program Operation and Internal Program Control Time.