Features
• Two LVCMOS/LVTTL outputs, 7 typical output impedance
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
• Internal bias on nCLK to support LVCMOS/LVTTL levels on CLK
input
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: -10ps ± 150ps (3.3V ± 5%)
• Full 3.3V or 2.5V operating supply
• 5V tolerant inputs
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Industrial temperature information available upon request