Features and benefits
 Dual 14-bit resolution
 650 Msps maximum update rate
 Selectable 2, 4 or 8 interpolation
filters
 Input data rate up to 160 Msps
 Very low noise cap-free integrated PLL
 32-bit programmable NCO frequency
 Dual port or Interleaved data modes
 1.8 V and 3.3 V power supplies
 LVDS compatible clock
 Two’s complement or binary offset data format
 3.3 V CMOS input buffers
 IMD3: 80 dBc; fs = 640 Msps; fo = 96 MHz
 ACPR: 71 dBc; 2 carriers WCDMA;
fs = 614.4 Msps; fo = 96 MHz; PLL on
 Typical 0.95 W power dissipation at 4
interpolation
 Power-down and Sleep modes
 Differential scalable output current from
1.6 mA to 22 mA
 On-chip 1.29 V reference
 External analog offset control
(10-bit auxiliary DACs)
 Internal digital offset control
 Inverse (sin x) / x function
 Fully compatible SPI port
 Industrial temperature range from
40 C to +85 C