Features
• Four low skew, low additive jitter LVPECL differential output pairs
• Differential LVPECL input pair can accept the following differential
input levels: LVDS, LVPECL, CML
• Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See the Applications section Writing the Differential Input
Levels to Accept Single-ended Levels (Figures 1 and 2)
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 5ps (typical)
• Propagation delay: 320ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 40fs (maximum)
• Maximum device current consumption (IEE): 60mA (maximum)
• Full 3.3V or 2.5V supply voltage
• Lead-free (RoHS 6) packaging
• -40°C to 85°C ambient operating temperature