Overview
The ISDN PC Adapter Circuit IPAC integrates all necessary functions for a host based ISDN access solution on a single chip.
It includes the S-transceiver (Layer 1), an HDLC controller for the D-channel and two protocol controllers for each B-channel. They can be used for HDLC protocol or transparent access. The system integration is simplified by several host interface configurations selected via pin strapping. They include multiplexed and demultiplexed interface options as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations.

Features
• Single chip host based ISDN solution
• Integrates S-transceiver, D-channel, B-channel
   protocol controller
• Replaces solutions based on ISAC-S TE PSB 2186
   and HSCX-TE PSB 21525
• Easy adjustment of software using ISAC-S and
   HSCX-TE
• Various types of protocol support depending on
   operating mode (Non-auto mode, transparent
   mode)
• Efficient transfer of data blocks from/to system
   memory by DMA or interrupt request
• Enlarged FIFO buffers (2x64 byte) per B-channel
   and per direction
• S-transceiver with TE, LT-S and LT-T modes
• D-channel FIFO buffers with 2x32byte
• D-channel access mechanism in all modes
• D-channel priority handler on IOM-2 for intelligent
   NT applications
• Software reset (required for Windows95)
• Programmable I/O interface with 2 interrupt inputs
• PCM interface for non IOM-2 compatible peripheral data controllers
• Programmable timer (1 ... 63 ms) for continuous or single interrupts
• Reduced register address space due to indirect address mode option
• 3 programmable LED outputs, one can indicate S bus activation status automatically
• 8-bit multiplexed or demultiplexed bus interface
• Siemens/Intel or Motorola µP interface