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TPMC630-20R Datasheet (PDF) - TEWS Technologies GmbH

TPMC630-20R Datasheet PDF - TEWS Technologies GmbH
Part # TPMC630-20R
Download  TPMC630-20R Download
File Size   123.31 Kbytes
Page   2 Pages
Manufacturer  TEWS [TEWS Technologies GmbH]
Direct Link  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH
Description Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O

TPMC630-20R Datasheet (PDF)

Go To PDF Page Download Datasheet
TPMC630-20R Datasheet PDF - TEWS Technologies GmbH

Part # TPMC630-20R
Download  TPMC630-20R Click to download

File Size   123.31 Kbytes
Page   2 Pages
Manufacturer  TEWS [TEWS Technologies GmbH]
Direct Link  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH
Description Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O

TPMC630-20R Datasheet (HTML) - TEWS Technologies GmbH


TPMC630-20R Product details

Application Information
The TPMC630 is a standard single-width 32 bit PMC module providing a user configurable FPGA with 300,000 (TPMC630-1x) or 600,000 (TPMC630-2x) system gates. All local signals from the PCI controller are routed to the FPGA.
The TPMC630-x0x has 64 ESD-protected TTL lines, the TPMC630-x1x provides 32 differential I/O lines using EIA-422 / EIA-485 compatible, ESD-protected line transceivers. The TPMC630-x2x provides 32 TTL and 16 differential I/Os. All lines are individually programmable as input or output. The receivers are always enabled, which allows determining the state of each I/O line at any time. This can be used as read back function for lines configured as outputs. Each TTL I/O line has a pull-up resistor. The pull-up voltage is selectable to be either +3.3V or +5V. The differential I/O lines are terminated by 120Ω resistors.
The FPGA is configured by a serial Flash. The Flash device is in-system programmable via driver software over the PCI bus. An in-circuit debugging option is available via an optionally mountable JTAG header (on the backside of the board) for readback and real-time debugging of the FPGA design (using Xilinx “ChipScope”).
A programmable clock generator supplies up to six different clock frequencies between 200 kHz and 166 MHz. All outputs are available at the FPGA, one clock source is in addition used as the local clock signal for the PCI controller. The clock generator settings are stored in an EEPROM and can be changed by the driver software through PCI9030 GPIO pins.
The configuration EEPROM of the PCI controller can also be modified by the driver software, to adapt address spaces etc.
User applications can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com.
The TPMC630 provides front panel I/O via a HD68 SCSI-3 type connector and rear panel I/O via P14.
For First Time Users the Engineering Documentation TPMC630-ED is recommended. The Engineering Documentation includes TPMC630-DOC, schematics, data sheets / application notes of the components and well documented sample VHDL source code.
Software Support (TPMC630-SW-xx) for different operating systems is available.




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