Function and Pinout Compatible With the
Fastest Bipolar Logic
25-Ω Output Series Resistors Reduce
Transmission-Line Reflection Noise
Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
3-State Outputs
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and
Output Logic Levels
12-mA Output Sink Current
15-mA Output Source Current

description
The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is
ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-Ω termination
resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the
CY74FCT373T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the
required setup times are latched when LE transitions from high to low. Data appears on the bus when the
output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode,
data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.