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SN75LVDS86ADGG Datasheet (PDF) - Texas Instruments

SN75LVDS86ADGG Datasheet PDF - Texas Instruments
Part # SN75LVDS86ADGG
Download  SN75LVDS86ADGG Download
File Size   518.55 Kbytes
Page   22 Pages
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments
Description FlatLink™ RECEIVER

SN75LVDS86ADGG Datasheet (PDF)

Go To PDF Page Download Datasheet
SN75LVDS86ADGG Datasheet PDF - Texas Instruments

Part # SN75LVDS86ADGG
Download  SN75LVDS86ADGG Click to download

File Size   518.55 Kbytes
Page   22 Pages
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments
Description FlatLink™ RECEIVER

SN75LVDS86ADGG Datasheet (HTML) - Texas Instruments


SN75LVDS86ADGG Product details

3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
Three Data Channels and Clock
Low-Voltage Differential Channels In and
21 Data and Clock Low-Voltage TTL
Channels Out
Operates From a Single 3.3-V Supply
Tolerates 4-kV HBM ESD
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
Consumes Less Than 1 mW When Disabled
Wide Phase-Lock Input Frequency Range
of 31 MHz to 68 MHz
No External Components Required for PLL
Inputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644
Standard
Improved Replacement for the DS90C364
and SN75LVDS86
Improved Jitter Tolerance
See SN65LVDS86A-Q1 Data Sheet for
Information About the Automotive
Qualified Version

description
The SN65LVDS86A/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers
and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions
allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over
four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data
at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. The
’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The
data bus appears the same at the input to the transmitter and output of the receiver with the data transmission
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level
on this signal clears all internal registers to a low level.
The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0C to 70C. The
SN65LVDS86A is characterized for operation over the full Automotive temperature range of −40°C to 125°C.




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