1FEATURES
23• Pin-to-Pin Compatible to DS90C383,
DS90C383A and DS90C385
• No Special Start-Up Sequence Required
between Clock/Data and /PD Pins. Input
Signals (Clock and Data) can be Applied Either
Before or After the Device is Powered.
• Support Spread Spectrum Clocking up to
100kHz Frequency Modulation and Deviations
of ±2.5% Center Spread or -5% Down Spread
• “Input Clock Detection" Feature Will Pull All
LVDS Pairs to Logic Low When Input Clock is
Missing and When /PD Pin is Logic High
• 18 to 87.5 MHz Shift Clock Support
• Tx Power Consumption < 147 mW (typ) at
87.5MHz Grayscale
• Tx Power-Down Mode < 60 μW (typ)
• Supports VGA, SVGA, XGA, SXGA(Dual Pixel),
SXGA+(Dual Pixel), UXGA(Dual Pixel).
• Narrow Bus Reduces Cable Size and Cost
• Up to 2.45 Gbps Throughput
• Up to 306.25Megabyte/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires No External Components
• Compliant to TIA/EIA-644 LVDS standard
• Low Profile 56-lead TSSOP Package

DESCRIPTION
The DS90C385A is a pin to pin compatible
replacement for DS90C383, DS90C383A and
DS90C385. The DS90C385A has additional features
and improvements making it an ideal replacement for
DS90C383, DS90C383A and DS90C385. family of
LVDS Transmitters.
The DS90C385A transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over the fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 87.5
MHz, 24 bits of RGB data and 3 bits of LCD timing
and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 612.5Mbps per LVDS data
channel. Using a 87.5 MHz clock, the data throughput
is 306.25Mbytes/sec. This transmitter can be
programmed for Rising edge strobe or Falling edge
strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a
Falling edge strobe FPDLink Receiver without any
translation logic.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high-speed TTL interfaces with added Spread Spectrum Clocking
support.