1 Features
1• 14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
• Noise Floor: –157 dBFS/Hz
• Spectral Performance (fIN = 170 MHz at –1 dBFS):
– SNR: 71.0 dBFS
– NSD: –155.9 dBFS/Hz
– SFDR: 85 dBc
– SFDR: 93 dBc (Except HD2, HD3, and
Interleaving Tones)
• Spectral Performance (fIN = 350 MHz at –1 dBFS):
– SNR: 69 dBFS
– NSD: –153.9 dBFS/Hz
– SFDR: 76 dBc
– SFDR: 90 dBc (Except HD2, HD3, and
Interleaving Tones)
• Channel Isolation: 100 dBc at fIN = 170 MHz
• Input Full-Scale: 1.9 VPP
• Input Bandwidth (3 dB): 1.2 GHz
• On-Chip Dither
• Integrated Wideband DDC Block
• JESD204B Interface with Subclass 1 Support:
– 2 Lanes per ADC at 6.25 Gbps
– 4 Lanes per ADC at 3.125 Gbps
– Support for Multi-Chip Synchronization
• Power Dissipation: 970 mW/Ch at 625 MSPS
• Package: 72-Pin VQFNP (10 mm × 10 mm)

2 Applications
• Radar and Antenna Arrays
• Broadband Wireless
• Cable CMTS, DOCSIS 3.1 Receivers
• Communications Test Equipment
• Microwave Receivers
• Software Defined Radio (SDR)
• Digitizers
• Medical Imaging and Diagnostics

3 Description
The ADS54J42 is a low-power, wide-bandwidth, 14-
bit, 625-MSPS, dual-channel, analog-to-digital
converter (ADC). Designed for high signal-to-noise
ratio (SNR), the device delivers a noise floor of
–157 dBFS/Hz for applications aiming for highest
dynamic range over a wide instantaneous bandwidth.
The device supports the JESD204B serial interface
with data rates up to 6.25 Gbps. The buffered analog
input provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold
glitch energy. Each ADC channel optionally can be
connected to a wideband digital down-converter
(DDC) block. The ADS54J42 provides excellent
spurious-free dynamic range (SFDR) over a large
input frequency range with very low power
consumption.
The JESD204B interface reduces the number of
interface lines, allowing high system integration
density. An internal phase-locked loop (PLL)
multiplies the ADC sampling clock to derive the bit
clock that is used to serialize the 14-bit data from
each channel.