1 Features
1• Quad Channel, 14-Bit Resolution
• Maximum Sampling Rate: 1 GSPS
• Maximum Output Sample Rate: 500 MSPS
• High-Impedance Analog Input Buffer
• Analog Input Bandwidth (–3 dB): 1 GHz
• Output Options:
– Digital Down Conversion (DDC) Using 16-Bit
NCO
– DDC Bypass With Full Rate Output Up to
500 MSPS
• Differential Full-Scale Input: 1.1 VPP
• JESD204B Interface:
– Subclass 1 Support
– 1 Lane per ADC Up to 10 Gbps
– Dedicated SYNC Pin for Pair of Channels
• Support for Multi-Chip Synchronization
• Spectral Performance:
– fIN = 190-MHz IF at –1 dBFS:
– SNR: 69 dBFS
– NSD: –153 dBFS/Hz
– SFDR: 86 dBc (HD2, HD3),
95 dBFS (Non HD2, HD3)
– fIN = 370-MHz IF at –3 dBFS:
– SNR: 68.5 dBFS
– NSD: –152.5 dBFS/Hz
– SFDR: 80 dBc (HD2, HD3),
86 dBFS (Non HD2, HD3)
• 72-Pin VQFN Package (10 mm × 10 mm)
• Power Consumption: 625 mW/Ch, 2.5 W Total
• Power Supplies: 1.15 V, 1.15 V, 1.9 V

2 Applications
• Multi-Carrier Multi-Mode, GSM Cellular
Infrastructure Base Stations
• Telecommunications Receivers
• Radar and Antenna Arrays
• Cable CMTS, DOCSIS 3.1 Receivers
• Communications Test Equipment
• Microwave Receivers
• Software Defined Radio (SDR)
• Digitizers
• Medical Imaging and Diagnostics

3 Description
The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering
wide-bandwidth, 2x oversampling and high SNR. The
ADS54J64 supports a JESD204B serial interface with
data rates up to 10 Gbps with one lane per channel.
The buffered analog input provides uniform
impedance across a wide frequency range and
minimizes sample-and-hold glitch energy. The
ADS54J64 provides excellent spurious-free dynamic
range (SFDR) over a large input frequency range with
very low power consumption. The digital signal
processing block includes complex mixers followed
by low-pass filters with decimate-by-2 and -4 options
supporting up to a 200-MHz receive bandwidth. The
ADS54J64 also supports a 14-bit, 500-MSPS output
in DDC bypass mode.
A four-lane JESD204B interface simplifies
connectivity, allowing high system integration density.
An internal phase-locked loop (PLL) multiplies the
incoming ADC sampling clock to derive the bit clock
that is used to serialize the 14-bit data from each
channel.