• 12 low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential CLK0, CLK1 pairs can accept the following
differential input levels: LVDS, CML
• Maximum input clock frequency: 1.5GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 10ps (typical)
• Propagation delay: 400ps (maximum)
• Low propagation delay variation across temperature for 1PPS applications
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz– 20MHz: 34fs (typical)
• Maximum device current consumption (IDD): 185mA typ at 1.8V
or 200mA typ at 2.5V
• Full 1.8V or 2.5V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFPN packaging
• -40°C to +85°C ambient operating temperature
• Supports case temperature up to +105°C
• Supports PCI Express Gen 1-5