• Four low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Applications Information, “Wiring the Differential Input
to Accept Single-Ended Levels” (Figures 1A and 1B)
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input, (input select)
• Output skew: 5ps (typical), at 3.63V
• Propagation delay: 200ps (typical), at 3.63V
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
• Maximum device current consumption (IEE): 60mA (maximum), at 3.63V
• Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
• Lead-free (RoHS 6), 16-Lead VFQFPN packaging
• -40°C to 85°C ambient operating temperature
• Supports case temperature  105°C operations
• Supports PCI Express Gen1–5