CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 8 of 44
4.0
Interface
4.1
Internal Masked ROM: 0xE800–0xFFFF
The CS5954AM has a built-in 3K×16 internal masked ROM that contains software bootstrap code to allow programs in an external
8-/16-bit ROM to be executed. The ROM code can also load data from the 2-wire serial interface into internal RAM for execution.
In addition, the internal BIOS ROM contains the interrupt service routines (see [Ref. 1] SL11R_BIOS for information) that support
the USB, 2-wire serial interface boot-up option (boot-up from 2-wire serial interface or external ROM). This CS5954AM BIOS
ROM eases software development of all CS5954AM interfaces. The CS5954AM chip is ready for all the USB enumeration and
download of program code.
The CS5954AM internal masked ROM (i.e. SL11R BIOS) is mapped from address 0xE800 to 0xFFFF. On power-up or hardware
reset, the CS5954AM processor jumps to the address of 0xFFF0, which contains a long jump to the beginning of the internal
ROM of address 0xE800. See Table 4-1.
4.2
External ROM: 0xC100–0xE800
The CS5954AM BIOS ROM reserves addresses from 0xC100 to 0xE800 for external ROM. During BIOS initialization, the
CS5954AM will scan for the signature ID (0xCB36) at location 0xC100. After a valid signature is detected, execution will begin
at address 0xC102 (see [Ref. 1] SL11R_BIOS for more information). The signal nXROMSEL is used to enable the external ROM.
It is mapped from 0xC100 to 0xE800 by default. However, the Extended Memory Control can be used to configure multiple
windows for external ROM set-up.[2]
4.3
Internal RAM: 0x0000–0x0BFF
The CS5954AM contains a 1.5K×16 internal RAM. This memory is used to buffer USB packets and is accessed by the 16-bit
processor and the SIE (Serial Interface Engine). USB transactions are automatically routed to the memory buffer. The CS5954AM
BIOS uses this internal RAM for USB buffers, BIOS variables and user data/code. Executable code or data can reside in multiple
locations: internal masked ROM (3K×16), internal RAM (3K×8), external ROM, and external SRAM. Program code or data can
also be loaded to either the internal or the external RAM from the USB port, the RS232 port, or the 2-wire serial interface.
The CS5954AM Internal RAM is mapped from 0x0000 to 0x0BFF. See internal RAM memory usage in Table 4-2 below.
• The addresses from 0x0000 to 0x00FF are reserved for hardware and software interrupt vectors (see [Ref. 1]
SL11R_BIOS for more information).
• Addresses from 0x0100 to 0x01FF are reserved for Internal Register Banks (CS5954AM register R0-R15 bank 0 and
R0-R15 bank 1) and the software stack. Others are reserved for USB Control registers and other read/write control
registers.
• Addresses from 0x0200 to 0x021F are reserved for the hardware interrupt stack.
• Addresses from 0x0220 to 0x0343 are available internal RAM for application software. Software can be downloaded
via the USB port (see [Ref. 1] SL11R_BIOS for more information).
Notes:
2.
The Address space from 0x8000-0xC100 can also be used as the external ROM (see the External Memory Control Set-up for more detail).
3.
This address may be changed due to CS5954AM BIOS revision updates. The new CS5954AM BIOS may require more internal memory for its variable usage
in any new CS5954AM BIOS.
Table 4-1. Internal Masked ROM (CS5954AM BIOS)
Address
Memory Description
0xE800
–0xFFEF
CS5954AM BIOS Code/Data Space
0xFFF0
–0xFFF3
Jump to 0xE800
0xFFF4
–0xFFF9
Reserved for Future Use
0xFFFA
–0xFFFB
ROM BIOS Checksum
0xFFFC
–0xFFFD
CS5954AM BIOS Revision
0xFFFE
–0xFFFE
Peripheral Revision
0xFFFF
–0xFFFF
QT Engine Instruction Revision
Table 4-2. Internal RAM Memory Usage
Address
Memory Description
0x0000
–0x00FF
Hardware/Software Interrupts
0x0100
–0x01FF
Register Banks/USB Control/Software Stack
0x0200
–0x021F
Hardware Interrupts Stack
0x0220
–0x0343[3]
CS5954AM BIOS Internal Buffers and Variables
0x0344
–0x0BFF
User’s Programming Space
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