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UPD16347 Datasheet(PDF) 21 Page - NEC |
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UPD16347 Datasheet(HTML) 21 Page - NEC |
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21 / 26 page  Data Sheet S16472EJ1V0DS 21 µµµµ PD16347 Timing Requirement (TA = 25 °°°°C, VDD1 = 4.75 to 5.25 V, VSS1 ==== VSS2 ==== VSS3 ==== 0 V, tr = tf ==== 3.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit Clock pulse width PWCLK 8ns Latch enable pulse width PW/LE 8ns Blank pulse width PW/BLK /HBLK, /LBLK 600 ns HZ pulse width PWHZ RL = 10 kΩ 3.3 µs /CLR pulse width PW/CLR 12 ns /CLR timing t/CLR 6ns Data setup time tSETUP 3ns Data hold time tHOLD 3ns Latch enable Time t/LE11, t/LE21 8ns t/LE12, t/LE22 8ns Detection Temperature Hysteresis Width and Detection Output DET output TDET MIN. Tj (˚C) Thys MIN. Note TDET MAX. Thys MAX.Note DET 10 k Ω VDD (Microcomputer side) To a microcomputer VSS3 to <Detection output circuit> Note Change of Thys linked with TDET's. "H" "L" 5 5 5 5 |
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