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CY29947
Document #: 38-07287 Rev. *C
Page 4 of 7
Notes:
5.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6.
Outputs driving 50
Ω transmission lines.
7.
50% input duty cycle.
8.
See Figure 2.
9.
Part-to-Part skew at a given temperature and voltage.
10. Set-up and hold times are relative to the falling edge of the input clock
AC Parameters[5]: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified temperature range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency[6]
VDD = 3.3V
200
MHz
VDD = 2.5V
170
Tpd
TCLK To Q Delay[6]
VDD = 3.3V
4.75
9.25
ns
VDD = 2.5V
6.50
10.50
FoutDC
Output Duty Cycle[6, 7]
Measured at VDD/2
45
55
%
tpZL, tpZH
Output Enable Time (all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
10
ns
Tskew
Output-to-Output Skew[6, 8]
150
250
ps
Tskew(pp)
Part-to-Part Skew[9]
2.0
ns
Ts
Set-up Time[6, 10]
SYNC_OE to TCLK
0.0
ps
Th
Hold Time[6, 10]
TCLK to SYNC_OE
1.0
ps
Tr/Tf
Output Clocks Rise/Fall Time[8]
0.8V to 2.0V,
VDD = 3.3V
0.20
1.0
ns
0.6V to 1.8V,
VDD = 2.5V
0.20
1.3
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