MSP432P411VIPZ datasheet(147/212 Pages) TI1

147 / 212 page

147

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

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The CRC16 computation signature is based on the CRC16-CCITT standard.

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The CRC32 computation signature is based on the CRC32-ISO 3309 standard.

6.9.13 AES256 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-

bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

6.9.14 True Random Seed

The Device Descriptor Information (TLV) contains a 128-bit true random seed that can be used to

implement a deterministic random number generator.

6.10 Code Development and Debug

MSP432P4x1x devices support various methods through which the user can carry out code development

and debug on the device.

6.10.1 JTAG and Serial Wire Debug (SWD) Based Development, Debug and Trace

The device supports both 4-pin JTAG and the 2-pin SWD modes of operation. The device is compatible

with all standard Cortex-M4 debuggers available in the market today. The debug logic in the device has

been designed to remain minimally intrusive to the application state. In low-power modes, the user can

enable the debugger to override the state of the PSS, thereby gaining access to debug and trace features.

In 2-pin SWD mode, the TDO pin can be used to export serial wire trace output (SWO) data. In addition,

the TDI and TDO pins of the device can be reassigned as user I/Os. See Section 6.12.24 and

Section 6.12.25 for more details.

NOTE

If the device has activated debug security, debugger accesses into the device is completely

disabled. The debugger, however, is still be able to scan the run/halt state of the CPU.

Further control of and visibility into the device is possible only after initiating a mass erase of

the device flash contents.

6.10.2 Peripheral Halt Control

The Peripheral Halt Control register in the System Controller module gives the user independent control

over the functionality of device peripherals during code development and debug. When the CPU is halted,

the bits in this register can control whether the corresponding peripheral freezes its operation (such as

incrementing, transmit, and receive) or continues its operation (debug remains nonintrusive). The registers

of the peripheral remain accessible without regard to the values in the Peripheral Halt Control register.

MSP432P411VIPZ Datasheet(PDF) 147 Page - Texas Instruments