SLG46121 datasheet(78/98 Pages) DIALOG

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SLG46121

16.0 Power On Reset (POR)

The SLG46121 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in

the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first

ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined

sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of

the I/O pins. This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during

the time while it is powering up and powering down.

16.1 General Operation

The SLG46121 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on PIN1) is less than 0.6V,

but not less than -0.6V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than

the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3V, applying a voltage higher than 0.3V to any other

PIN is incorrect, and can lead to incorrect or unexpected device behavior.

Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes.

To start the POR sequence in the SLG46121, the voltage applied on the VDD should be higher than the Power_ON threshold

(see Note 2). The full operational VDD range for the SLG46121 is 1.71 V – 5.5 V (1.8 V ± 10% - 5 V ± 10%). This means that the

VDD voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage

rises to the Power_ON threshold. After the POR sequence has started, the SLG46121 will have a typical period of time to go

through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after

the POR sequence is complete.

Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6 V.

To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it

should be less than 0.6 V.

All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step

in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin

configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage

on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

Note that VDD2 has no influence on POR sequence, all internal macrocells are powered from VDD. It means, VDD2 can be

switched on/off while VDD is on. If voltage on VDD2 appears after the POR sequence, pins 8, 9, 10, 12 become available when

VDD2 reaches 0.6 V.

For proper power up sequence, make sure VDD2 will not exceed VDD at any point during startup.

For normal operation VDD should not be switched off while VDD2 is on, due to VDD2≤VDD,see section 5.0 Electrical Specifica-

tions.

SLG46121 Datasheet(PDF) 78 Page - Dialog Semiconductor