SLG46580 datasheet(92/194 Pages) DIALOG

92 / 194 page

SLG46580/82/83_DS_062

Page 91 of 193

SLG46580/82/83

Preliminary

11.6 ACMP2 Register Settings

Table 65. ACMP2 Register Settings

Signal Function

Address

ACMP2 Positive Input

Source Select -

ACMP0 IN+ Source

reg<1124>

0: Disable

1: Enable

ACMP2 Hysteresis

Enable

reg<1127:1125> 000: 0 mV

001: 25 mV

010: 50 mV

011: 200 mV

100: Reserved

101: Reserved

110: 100 mV

111: 150 mV

(001: for both external & internal VREF, 010 & 011 & 110 & 111: for only internal

VREF,

External VREF will not have 50 mV, 100 mV, 150 mV & 200 mV hysteresis.)

ACMP2 Wake & Sleep

function Enable

reg<1444>

0: Disable

1: Enable

TS output connection

enable to ACMP2

reg<1493>

0: Default ACMP function

1: Enable TS function

ACMP2 In Voltage

Select

reg<1644:1640>

00000: 50 mV

00001: 100 mV

00010: 150 mV

00011: 200 mV

00100: 250 mV

00101: 300 mV

00110: 350 mV

00111: 400 mV

01000: 450 mV

01001: 500 mV

01010: 550 mV

01011: 600 mV

01100: 650 mV

01101: 700 mV

01110: 750 mV

01111: 800 mV

10000: 850 mV

10001: 900 mV

10010: 950 mV

10011: 1 V

10100: 1.05 V

10101: 1.1 V

10110: 1.15 V

10111: 1.2 V

11000: VDD: ACMP2- /3

11001: VDD: ACMP2- /4

11010: IO6: EXT_VREF

11011: IO6: EXT_VREF /2

ACMP2 Positive Input

Divider

reg<1646:1645> 00: 1.00X

01: 0.50X

10: 0.33X

11: 0.25X

ACMP2 Low

Bandwidth (Max: 1

MHz) Enable

reg<1647>

0: Off

1: On

SLG46580 Datasheet(PDF) 92 Page - Dialog Semiconductor

SLG46580 Datasheet(HTML) 92 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL