AD8285CP-EBZ datasheet(19/28 Pages) AD

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AD8285

Data Sheet

Rev. B | Page 18 of 27

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD8285. This is gained up internally by a factor of 2, setting

VREF to 1.024 V, which results in a full-scale differential input

span of 2.0 V p-p for the ADC. VREF is set internally by default,

but the VREF pin can be driven externally with a 1.0 V reference to

achieve more accuracy. However, this device does not support

ADC full-scale ranges below 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin, use

ceramic low ESR capacitors. These capacitors must be close to

the reference pin and on the same layer of the printed circuit board

(PCB) as the AD8285. The VREF pin must have both a 0.1 μF

capacitor and a 1 μF capacitor connected in parallel to the analog

ground. These capacitor values are recommended for the ADC

to properly settle and acquire the next valid sample.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD8285, it is recommended

that two separate 1.8 V supplies and two separate 3.3 V supplies

be used: one supply each for analog 1.8 V (AVDD18x), digital

1.8 V (DVDD18x), analog 3.3 V (AVDD33x), and digital 3.3 V

(DVDD33x). If only one supply is available for both analog and

digital, for example, AVDD18x and DVDD18x, route the supply

to the AVDD18x first and then tap off and isolate it with a ferrite

bead or a filter choke preceded by decoupling capacitors for the

DVDD18x. The same is true for the analog and digital 3.3 V

supplies.

Use several decoupling capacitors on all supplies to cover both

high and low frequencies. Locate these capacitors close to the

point of entry at the PCB level and close to the device, with

minimal trace lengths.

When using the AD8285, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the analog,

digital, and clock sections of the PCB, optimum performance

can be achieved easily.

EXPOSED PADDLE THERMAL HEAT SLUG

RECOMMENDATIONS

It is required that the exposed paddle on the underside of the

device be connected to a quiet analog ground to achieve the

best electrical and thermal performance of the AD8285. Mate

an exposed continuous copper plane on the PCB to the AD8285

exposed paddle, Pin 0. The copper plane must have several vias

to achieve the lowest possible resistive thermal path for heat

dissipation to flow through the bottom of the PCB. Fill or plug

these vias with nonconductive epoxy.

To maximize the coverage and adhesion between the device and

the PCB, partition the continuous copper pad by overlaying a

silkscreen or solder mask to divide the copper pad into several

uniform sections. Dividing the copper pad ensures several tie

points between the PCB and the EPAD during the reflow process.

Using one continuous plane with no partitions only guarantees

one tie point between the AD8285 and the PCB. For more detailed

information on packaging, and for more PCB layout examples,

see the AN-772 Application Note.

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