ADATE318BCPZ datasheet(52/81 Pages) AD

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Data Sheet

ADATE318

Rev. B | Page 51 of 80

RESET SEQUENCE AND THE RST PIN

The internal state of the ADATE318 is indeterminate following

power-up. For this reason, it is necessary to perform a complete

reset sequence once the power supplies have stabilized. Further,

the RST pin must be held in the asserted state before and during

the power-up sequence and released only after all power supplies

are known to be stable.

The ADATE318 has an active low pin (RST) that asynchron-

ously starts a reset sequence. A soft reset sequence can also be

initiated under SPI software control by writing to the

SPI_RESET bit in the SPI Control Register (SPI 0x12[0] (see

Figure 13)). In the case of a soft reset, the sequence begins on

the first rising edge of SCLK following the release of CS, subject

to the normal setup and hold times. Certain actions take place

immediately upon initiation of the reset request, whereas other

actions require SCLK.

The following asynchronous actions take place as soon as a

reset request is detected, whether or not SCLK is active:



Assert BUSY pin



Force all control registers to the default reset state as

defined by control register definitions



Clear all calibration registers to the default reset state as

defined by calibration register definitions



Override all DAC output voltages and force analog levels to

VDUTGND



Disable DCLs and PPMUs; open system PMU switches



Soft connect the DUT0 and DUT1 pins to VDUTGND (see

Figure 114)

The part remains in this static reset state indefinitely until the

clocked portion of the sequence begins with either the first

rising edge of SCLK following the release of RST (asynch-

ronous reset) or the second rising edge of SCLK following the

release of CS (soft reset). No matter how the reset sequence is

initiated, the clocked portion of the reset sequence requires 64

SCLK cycles to run to completion, and the BUSY pin remains

asserted until these clock cycles have been received. The

following actions take place during the clocked portion of the

reset sequence:



Complete internal SPI controller initialization



Write the appropriate values to specific DAC X2 registers

(see Table 19)



Enable the thermal alarm with a 100C threshold; disable

PPMU and the overvoltage detect (OVD) alarms

The 64th rising edge of SCLK releases BUSY and starts a self-

timed DAC deglitch period of approximately 3 μs. DAC voltages

begin to change once the deglitch circuits have timed out, and

they then require an additional 10 μs to settle to their final

values. Thus, a full reset sequence requires approximately 15 μs,

comprising 1.28 μs (64 cycles  20 ns) for the reset state

machine, 3 μs for DAC deglitch, and another 10 μs for settling.

DRIVER

DUTGND

DUTx

COMPARATORS

50Ω

10kΩ

CLAMPS

TO PPMU

LOAD

DUT PULLDOWNx

ADDR 0x19[7]

DUT PULL-DOWN SWITCH DEFAULTS TO A

CLOSED STATE IMMEDIATELY FOLLOWING

AN ASSERT OF RST (FOR HARD RESET)

OR AT THE FIRST RISING EDGE OF SCLK

FOLLOWING THE SPI CS (FOR SOFT RESET).

SEE DCL CONTROL REGISTER 0x19[7].

Figure 114. DUTx to VDUTGND Soft Connect Detail

ADATE318BCPZ Datasheet(PDF) 52 Page - Analog Devices

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