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LTC5100EUF Datasheet(PDF) 47 Page - Linear Technology |
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LTC5100EUF Datasheet(HTML) 47 Page - Linear Technology |
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47 / 52 page ![]() LTC5100 47 sn5100 5100fs APPLICATIO S I FOR ATIO HIGH SPEED DESIGN AND LAYOUT Figure 29 and Figure 30 show the schematic and layout of a minimum component count circuit for standalone op- eration. The exposed pad of the package is soldered to a copper pad on top of the board, and nine vias couple this pad to the ground plane. The four VSS pins (Pins 1, 4, 9, and 12) have webs of copper connecting them to the cen- tral pad to reduce ground inductance. The laser modula- tion current returns to the ground plane primarily through the exposed pad. Any measures that reduce the induc- tance from the pad to the ground plane improve the modu- lation waveforms and reduce RFI. FAULT SDA SCL VDD(HS) VDD VSS IN+ IN– VSS VSS MODA MODB VSS EN SRC LTC5100 MD 13 12 R1 50 Ω C1 10nF ZO = 50Ω 11 10 9 1 L1 FERRITE BEAD ENABLE +TX_DATA –TX_DATA FAULT VDD + 3.3V VSS 2 3 4 14 15 16 8 FIBER C3 10nF 24LC00 EEPROM SOT23 PACKAGE PROGRAMMING PADS 5100 F29 7 6 5 ZO = 50Ω VCC NC SCL VSS SDA IN+ VSS IN– EEPROM C1 R1 L1 C3 2 3 VSS VSS 5100 F30 MODA MODB 1 16 15 14 13 VSS 4 11 10 12 9 5678 SCL VCC VSS SDA NC Figure 29. Schematic of a Minimum Component Count Circuit Figure 30. Layout of the Minimum Component Count Circuit Using 0402 Passive Components |
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