AD9874EB datasheet(17/40 Pages) AD

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REV. 0

AD9874

–17–

The AD9874 also provides the means for controlling the switching

characteristics of the digital output signals via the DS (drive

strength) field of the SSICRB. This feature is useful in limiting

switching transients and noise from the digital output that may

ultimately couple back into the analog signal path, potentially

degrading the AD9874’s sensitivity performance. Figures 3c and

3d show how the NF can vary as a function of the SSI setting for

an IF frequency of 109.65 MHz. The following two observations

can be made from these figures:

• The NF becomes more sensitive to the SSI output drive strength

level at higher signal bandwidth settings.

• The NF is dependent on the number of bits within an SSI frame,

becoming more sensitive to the SSI output drive strength level

as the number of bits is increased. As a result, one should select

the lowest possible SSI drive strength setting that still meets

the SSI timing requirements.

SSI OUTPUT DRIVE STRENGTH SETTING

10.0

9.6

8.0

24-BIT I/O DATA

9.8

9.4

9.2

9.0

8.6

8.8

8.4

8.2

16-BIT I/O DATA

w/DVGA ENABLED

16-BIT I/O DATA

Figure 3c. NF vs. SSI Output Drive Strength

(VDDx = 3.0 V, fCLK = 18 MSPS, BW = 10 kHz)

SSI OUTPUT DRIVE STRENGTH SETTING

24-BIT I/O DATA

16-BIT I/O DATA

w/DVGA ENABLED

16-BIT I/O DATA

Figure 3d. NF vs. SSI Output Drive Strength

(VDDx = 3.0 V, fCLK = 18 MSPS, BW = 75 kHz)

Table V lists the typical output rise/fall times as a function of

DS for a 10 pF load. Rise/fall times for other capacitor loads can

be determined by multiplying the typical values presented in

Table V by a scaling factor equal to the desired capacitive load

divided by 10 pF.

*Blackfin is a registered trademark of Analog Devices, Inc.

Table V. Typical Rise/Fall times (

±25 %) with a 10 pF

Capacitive Load for Each DS Setting

typ (ns)

013.5

7.2

5.0

3.7

3.2

2.8

2.3

2.0

Synchronization

Applications, such as receiver diversity, employing more than

one AD9874 device may desire synchronization of the digital

output data. SYNCB can be used for this purpose and applied

upon system initialization. It is an active-low signal that clears

the clock counters in both the decimation filter and the SSI

port. The counters in the clock synthesizers are not reset, since

it is presumed that the CLK signals of multiple chips would be

connected together. SYNCB also clears the registers in the

decimation filter and resets the modulator. As a result, valid

data representative of the input signal will be available once the

digital filters have been flushed.

Figure 4a shows the timing relationship between SYNCB and the

SSI port’s CLKOUT and FS signals. SYNCB is an asynchronous

active-low signal that must remain low for at least half an input

clock period (i.e., 1/(2

× f

CLK) ). CLKOUT returns high while

FS remains low upon SYNCB going low. CLKOUT will become

active within 1 to 2 output clock periods upon SYNCB returning

high. FS will reappear several output clock cycles later, depend-

ing on the digital filter’s decimation factor and the SSIORD

setting. To verify proper synchronization, the FS signals of the

multiple AD9874 devices should be monitored.

SYNCB

CLKOUT

Figure 4a. SYNCB Timing

INTERFACING TO DSPs

The AD9874 connects directly to an Analog Devices program-

mable digital signal processor (DSP). Figure 4b illustrates an

example with the Blackfin

® series of ADSP-2153x processors.

The Blackfin DSP series is a family of 16-bit products optimized

for telecommunications applications with its dynamic power

management feature making it well suited for portable radio

products. The code compatible family members share the funda-

mental core attributes of high performance, low power consumption,

and the ease-of-use advantages of microcontroller instruction set.

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