DS90CF581 Pin DescriptionFPD Link Transmitter

Pin Name

IO

No

Description

TxIN

I

28

TTL level input This includes 8 Red 8 Green 8 Blue and 4 control lines (FPLINE FPFRAME

DRDY CNTL) (Also referred to as HSYNC VSYNC and DATA ENABLE)

O

4

Positive LVDS differential data output

O

4

Negative LVDS differential data output

FPSHIFT IN

I

1

TTL level clock input The falling edge acts as data strobe

O

1

Positive LVDS differential clock output

O

1

Negative LVDS differential clock output

PWR DOWN

I

1

TTL level input Assertion (low input) TRI-STATE the outputs ensuring low current at power down

I

4

Power supply pins for TTL inputs

GND

I

5

Ground pins for TTL inputs

I

1

Power supply pin for PLL

PLL GND

I

2

Ground pins for PLL

I

1

Power supply pin for LVDS outputs

LVDS GND

I

3

Ground pins for LVDS outputs

DS90CF582 Pin DescriptionFPD Link Receiver

Pin Name

IO

No

Description

I

4

Positive LVDS differential data inputs

I

4

Negative LVDS differential data inputs

RxOUT

O

28

TTL level data outputs This includes 8 Red 8 Green 8 Blue and 4 control lines (FPLINE

FPFRAME DRDY CNTL) (Also referred to as HSYNC VSYNC and DATA ENABLE)

I

1

Positive LVDS differential clock input

I

1

Negative LVDS differential clock input

FPSHIFT OUT

O

1

TTL level clock output The falling edge acts as data strobe

PWR DOWN

I

1

TTL level input Assertion (low input) maintains the receiver outputs in the previous state

I

4

Power supply pins for TTL outputs

GND

I

5

Ground pins for TTL outputs

I

1

Power supply pin for PLL

PLL GND

I

2

Ground pin for PLL

I

1

Power supply pin for LVDS inputs

LVDS GND

I

3

Ground pins for LVDS inputs

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