FDMF5833 datasheet(16/25 Pages) ONSEMI

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Zero Cross Detect (ZCD) Operation

The ZCD control block houses the circuitry that

determines when the inductor current reverses direction

and controls when to turn off the low-side MOSFET. A

low offset comparator monitors the SW-to-PGND

voltage of the low-side MOSFET during the LS

MOSFET on-time. When the sensed voltage switches

polarity from negative to positive, the comparator

changes state and reverse current has been detected.

This comparator offset must sense the negative VSW

within a 0.5 mV worst-case range. The negative offset

is to ensure the inductor current never reverses; some

small body-diode conduction is preferable to having

negative current.

The comparator is switched on after the rising edge of

the low-side gate drive and turned off by the signal at

the input to the low-side gate driver. In this way, the

zero-current comparator is connected with a break-

before-make connection, allowing the comparator to be

designed with all low-voltage transistors.

PWM

ZCD#

GH to

Inductor

Current

(simplified

slopes)

(zoom)

VIH_ZCD#

tPD_PHGLL

VIL_ZCD#

VIH_PWM

VIL_PWM

10%

90%

10%

tD_DEADON

tPD_PLGHL

tD_DEADOFF

tPD_PHGLL

tD_DEADON2

tPD_ZCD

10%

90%

tPD_PHGHH

10%

Delay from PWM going

HIGH to HS VGS HIGH

(HS turn-on in DCM)

90%

10%

90%

tPD_ZHGLH

tPD_ZLGLL

Delay from ZCD# going

HIGH to LS VGS HIGH

Delay from ZCD# going

LOW to LS VGS LOW

VIN

VOUT

CCM

(Negative inductor current)

DCM

CCM operation with

positive inductor current

CCM operation with

negative inductor current

DCM operation: Diode

Emulation using the GL (LS

MOSFET VGS) to eliminate

negative inductor current

DCM operation: Diode

Emulation using the GL (LS

MOSFET VGS) to eliminate

negative inductor current

ZCD# used to

control negative

inductor current

(fault condition)

VZCD_OFF :

-0.5mV

Figure 36.

ZCD# & PWM Timing Diagram

Thermal Warning Flag (THWN#)

The FDMF5833 provides a thermal warning (THWN) for

over-temperature conditions. The THWN flag pulls

THWN# pin LOW (to AGND) if the driver IC detects the

125°C activation temperature. The THWN# pin output

returns to high-impedance state once the temperature

falls to the 110°C reset temperature. Figure 37 shows

the THWN# operation. THWN does not disable the SPS

module and works independently of other features.

The THWN mode of operation requires a pull-up resistor

to VCC rail. THWN# flag is active LOW.

Thermal Shutdown (THDN)

A programmed thermal shutdown engages once the

driver TJ reaches 150°C. The shutdown event is a

latched shut down, where the THDN signal clocks the

fault latch and physically pulls down the EN pin.

Recycling 5 V VCC (POR event) is required to re-enable

the driver IC.

Figure 37.

Gate Driver TJ vs. VTHWN#

FDMF5833 Datasheet(PDF) 16 Page - ON Semiconductor

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